Level B - Semi-empirical Model

Level B extends the analytical model with short-channel effects (SCE) and semi-empirical corrections. It provides more realistic results for modern scaled transistors while maintaining computational efficiency.

Short-Channel Effects Overview

As MOSFET dimensions shrink, several non-ideal effects become significant:

Effect	Physical Origin	Impact on Device
Velocity Saturation	High lateral field	Reduced current, earlier saturation
DIBL	Drain field penetration	Lower Vth, higher Ioff
CLM	Pinch-off movement	Non-zero output conductance
Mobility Degradation	Vertical field scattering	Reduced current
Hot Carriers	High-energy electrons	Reliability degradation

1. Velocity Saturation

At high lateral electric fields ( ), carrier velocity saturates:

Modified Saturation Voltage

With velocity saturation, the device saturates at a lower voltage:

Where is the saturation field (~0.8 V/μm for electrons).

Short-Channel Impact

For a 45nm device with = 0.4V:

• Long-channel: = 0.4V
• With velocity sat: ≈ 0.25V

The device saturates earlier and at lower current.

Saturation Current

For very short channels, this approaches:

Note: Current becomes linear with instead of quadratic!

2. DIBL (Drain-Induced Barrier Lowering)

The drain electric field penetrates into the channel, lowering the source-channel barrier:

Where is the DIBL coefficient (typically 20-200 mV/V).

DIBL Scaling

DIBL worsens with shorter channels:

Where is the characteristic length:

Design Rule

To maintain good SCE control:

For a 45nm process: ≈ 1.5nm, ≈ 30nm → ≈ 12nm

3. Channel Length Modulation (CLM)

In saturation, the pinch-off point moves toward the source as increases:

Output Conductance

CLM causes non-zero output conductance in saturation:

This limits voltage gain in analog circuits:

CLM Coefficient

Typical values: = 0.05-0.2 V⁻¹ for 45nm technology.

4. Body Effect

Back-bias voltage affects threshold voltage:

	Δ (γ=0.4)
0 V	0 mV
0.5 V	85 mV
1.0 V	150 mV

Reverse Body Bias

Applying increases , which:

• Reduces leakage (good for standby)
• Decreases (bad for performance)

This is used for dynamic threshold adjustment in low-power designs.

5. Mobility Degradation

Vertical Field Effect

The gate electric field pushes carriers against the Si/SiO₂ interface, increasing scattering:

Where V⁻¹ for electrons.

Combined Mobility Model

Level B uses a unified mobility model:

• : Coulomb scattering (dominant at low )
• : Surface roughness (dominant at high )

6. Subthreshold Swing Degradation

Interface traps and short-channel effects increase SS:

Where the body factor becomes:

Technology	Typical SS
180nm	80-90 mV/dec
65nm	90-100 mV/dec
28nm	100-110 mV/dec

Complete Level B Current Model

The full drain current model combines all effects:

Where:

• includes vertical field degradation
• accounts for velocity saturation
• models CLM

Extracted Metrics

Level B provides additional device metrics:

Metric	Definition	Typical Range
DIBL		50-150 mV/V
SS		70-110 mV/dec
	Peak transconductance	0.5-2 mS/μm
	Output resistance	1-10 kΩ·μm
	Current ratio	10⁵-10⁷

When to Use Level B

✅ Good for:

• Device design and optimization
• Short-channel device analysis (L > 20nm)
• Process technology comparisons
• Understanding SCE tradeoffs
• Circuit-level simulations
• Analog design insights

❌ Not suitable for:

• Ultra-short channels (L < 20nm)
• Accurate leakage prediction
• Hot carrier reliability
• Quantum effects analysis

Comparison: Level A vs Level B

Aspect	Level A	Level B
Velocity saturation	❌	✅
DIBL	❌	✅
CLM	❌	✅
Body effect	✅ (basic)	✅ (enhanced)
Mobility degradation	❌	✅
Computation time	~1 ms	~2 ms
Accuracy (45nm)	Poor	Good

For accurate device characterization of advanced nodes, consider Level C - Numerical Model.