Device Parameters
This guide explains all the device parameters available in the simulator and their effects on device performance.
Gate Stack
Oxide Thickness ( )
| Property | Value |
|---|---|
| Range | 0.5 - 10 nm |
| Default | 2 nm |
| Unit | nm |
Physical Significance:
The gate oxide thickness directly affects oxide capacitance:
Effects:
| Lower | Higher |
|---|---|
| ↑ Gate capacitance | ↓ Gate capacitance |
| ↑ Drive current | ↓ Drive current |
| ↓ Threshold voltage | ↑ Threshold voltage |
| ↑ Gate leakage | ↓ Gate leakage |
| Better SCE control | Worse SCE control |
Scaling Limits
Below ~1.5nm (SiO₂), direct tunneling becomes significant. Modern processes use high-k dielectrics (HfO₂) to maintain physical thickness while achieving low EOT.
Channel Length ( )
| Property | Value |
|---|---|
| Range | 20 - 500 nm |
| Default | 90 nm |
| Unit | nm |
Physical Significance:
Channel length determines current capacity and short-channel susceptibility:
Effects:
| Shorter L | Longer L |
|---|---|
| ↑ Current density | ↓ Current density |
| ↑ Speed (lower RC) | ↓ Speed |
| ↑ SCE (DIBL, Vth roll-off) | ↓ SCE |
| ↑ Leakage | ↓ Leakage |
Gate Work Function ( )
| Property | Value |
|---|---|
| Range | 4.0 - 5.5 eV |
| Default | 4.15 eV (n+ poly), 5.25 eV (p+ poly) |
| Unit | eV |
Common Materials:
| Material | Work Function (eV) | Use |
|---|---|---|
| n+ poly-Si | 4.05 - 4.15 | nMOS |
| p+ poly-Si | 5.15 - 5.25 | pMOS |
| TiN | 4.4 - 4.6 | nMOS (HKMG) |
| TaN | 4.8 - 5.0 | pMOS (HKMG) |
Effect on Threshold:
Adjusting shifts approximately 1:1.
Channel
Channel Doping ( )
| Property | Value |
|---|---|
| Range | 10¹⁵ - 10¹⁹ cm⁻³ |
| Default | 5×10¹⁷ cm⁻³ |
| Unit | cm⁻³ |
Physical Significance:
Channel doping sets the body charge that must be depleted to form an inversion layer:
Effects:
| Higher | Lower |
|---|---|
| ↑ Threshold voltage | ↓ Threshold voltage |
| ↓ DIBL | ↑ DIBL |
| ↓ Mobility (scattering) | ↑ Mobility |
| ↑ Body effect | ↓ Body effect |
| ↓ Depletion width | ↑ Depletion width |
Design Trade-off
High channel doping improves SCE control but degrades mobility. Modern devices use retrograde doping (low surface, high subsurface) for optimal trade-off.
Doping Profile Type
| Option | Description |
|---|---|
| Uniform | Constant doping throughout channel |
| Retrograde | Low surface doping, peak below surface |
| SSR | Super-steep retrograde |
Source/Drain
S/D Doping ( )
| Property | Value |
|---|---|
| Range | 10¹⁸ - 10²¹ cm⁻³ |
| Default | 10²⁰ cm⁻³ |
| Unit | cm⁻³ |
Physical Significance:
High S/D doping reduces:
- Contact resistance
- Series resistance
- Junction built-in potential
Effects:
| Higher | Lower |
|---|---|
| ↓ Series resistance | ↑ Series resistance |
| ↓ Contact resistance | ↑ Contact resistance |
| ↑ Junction capacitance | ↓ Junction capacitance |
| ↑ Band-to-band tunneling | ↓ Tunneling |
Junction Depth ( )
| Property | Value |
|---|---|
| Range | 10 - 200 nm |
| Default | 50 nm |
| Unit | nm |
Physical Significance:
Junction depth affects the characteristic length:
Good SCE control requires .
Effects:
| Shallower | Deeper |
|---|---|
| ↓ SCE | ↑ SCE |
| ↑ Series resistance | ↓ Series resistance |
| ↓ Junction capacitance | ↑ Junction capacitance |
LDD Doping ( )
| Property | Value |
|---|---|
| Range | 10¹⁷ - 10²⁰ cm⁻³ |
| Default | 5×10¹⁸ cm⁻³ |
| Unit | cm⁻³ |
Purpose:
Lightly Doped Drain (LDD) extensions:
- Reduce peak electric field at drain
- Mitigate hot carrier effects
- Improve reliability
LDD Length ( )
| Property | Value |
|---|---|
| Range | 5 - 50 nm |
| Default | 20 nm |
| Unit | nm |
Trade-offs:
| Longer LDD | Shorter LDD |
|---|---|
| ↓ Peak E-field | ↑ Peak E-field |
| ↑ Series resistance | ↓ Series resistance |
| Better HCI immunity | Worse HCI immunity |
Substrate
Substrate Doping ( )
| Property | Value |
|---|---|
| Range | 10¹⁴ - 10¹⁸ cm⁻³ |
| Default | 10¹⁷ cm⁻³ |
| Unit | cm⁻³ |
Physical Significance:
Sets the body effect coefficient:
And depletion width:
Geometry
Channel Width ( )
| Property | Value |
|---|---|
| Range | 50 - 2000 nm |
| Default | 360 nm (nMOS), 720 nm (pMOS) |
| Unit | nm |
Physical Significance:
Width directly scales current:
PMOS Sizing
PMOS is typically 2× wider than NMOS to compensate for lower hole mobility:
Gate-S/D Overlap ( )
| Property | Value |
|---|---|
| Range | 0 - 20 nm |
| Default | 5 nm |
| Unit | nm |
Effects:
- Contributes to overlap capacitance:
- Affects Miller effect in switching
- Reduces effective channel length
Advanced Parameters
Fixed Oxide Charge ( )
| Property | Value |
|---|---|
| Range | ±10¹² cm⁻² |
| Default | 0 |
| Unit | cm⁻² |
Effect:
Shifts flat-band and threshold voltage:
Positive charge shifts negative.
Interface Trap Density ( )
| Property | Value |
|---|---|
| Range | 0 - 10¹³ cm⁻² eV⁻¹ |
| Default | 0 |
| Unit | cm⁻² eV⁻¹ |
Effects:
- Increases subthreshold swing
- Causes frequency dispersion in C-V
- Degrades mobility (Coulomb scattering)
Series Resistance ( , )
| Property | Value |
|---|---|
| Range | 0 - 1000 Ω |
| Default | 0 |
| Unit | Ω |
Effects:
- Reduces effective :
- Limits maximum current
- Causes negative feedback
Components:
- Contact resistance
- Silicide resistance
- LDD resistance
- Spreading resistance
Parameter Scaling Guidelines
For scaling to a new technology node:
| Parameter | Scaling Factor | 45nm → 28nm |
|---|---|---|
| 0.7× | 45 → 28 nm | |
| 0.7× | 180 → 120 nm | |
| 0.8× | 1.5 → 1.2 nm | |
| 0.9× | 1.0 → 0.9 V | |
| 0.7× | 30 → 20 nm | |
| 1.4× | 10¹⁸ → 2×10¹⁸ cm⁻³ |
Non-Ideal Scaling
Real scaling is constrained by:
- Gate leakage (can't scale indefinitely)
- Threshold variation (limits scaling)
- Power density (thermal limits)