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Device Parameters ​

This guide explains all the device parameters available in the simulator and their effects on device performance.

Gate Stack ​

Oxide Thickness ( ) ​

PropertyValue
Range0.5 - 10 nm
Default2 nm
Unitnm

Physical Significance:

The gate oxide thickness directly affects oxide capacitance:

Effects:

Lower Higher
↑ Gate capacitance↓ Gate capacitance
↑ Drive current↓ Drive current
↓ Threshold voltage↑ Threshold voltage
↑ Gate leakage↓ Gate leakage
Better SCE controlWorse SCE control

Scaling Limits

Below ~1.5nm (SiO₂), direct tunneling becomes significant. Modern processes use high-k dielectrics (HfO₂) to maintain physical thickness while achieving low EOT.

Channel Length ( ) ​

PropertyValue
Range20 - 500 nm
Default90 nm
Unitnm

Physical Significance:

Channel length determines current capacity and short-channel susceptibility:

Effects:

Shorter LLonger L
↑ Current density↓ Current density
↑ Speed (lower RC)↓ Speed
↑ SCE (DIBL, Vth roll-off)↓ SCE
↑ Leakage↓ Leakage

Gate Work Function ( ) ​

PropertyValue
Range4.0 - 5.5 eV
Default4.15 eV (n+ poly), 5.25 eV (p+ poly)
UniteV

Common Materials:

MaterialWork Function (eV)Use
n+ poly-Si4.05 - 4.15nMOS
p+ poly-Si5.15 - 5.25pMOS
TiN4.4 - 4.6nMOS (HKMG)
TaN4.8 - 5.0pMOS (HKMG)

Effect on Threshold:

Adjusting shifts approximately 1:1.

Channel ​

Channel Doping ( ) ​

PropertyValue
Range10¹⁵ - 10¹⁹ cm⁻³
Default5×10¹⁷ cm⁻³
Unitcm⁻³

Physical Significance:

Channel doping sets the body charge that must be depleted to form an inversion layer:

Effects:

Higher Lower
↑ Threshold voltage↓ Threshold voltage
↓ DIBL↑ DIBL
↓ Mobility (scattering)↑ Mobility
↑ Body effect↓ Body effect
↓ Depletion width↑ Depletion width

Design Trade-off

High channel doping improves SCE control but degrades mobility. Modern devices use retrograde doping (low surface, high subsurface) for optimal trade-off.

Doping Profile Type ​

OptionDescription
UniformConstant doping throughout channel
RetrogradeLow surface doping, peak below surface
SSRSuper-steep retrograde

Source/Drain ​

S/D Doping ( ) ​

PropertyValue
Range10¹⁸ - 10²¹ cm⁻³
Default10²⁰ cm⁻³
Unitcm⁻³

Physical Significance:

High S/D doping reduces:

  • Contact resistance
  • Series resistance
  • Junction built-in potential

Effects:

Higher Lower
↓ Series resistance↑ Series resistance
↓ Contact resistance↑ Contact resistance
↑ Junction capacitance↓ Junction capacitance
↑ Band-to-band tunneling↓ Tunneling

Junction Depth ( ) ​

PropertyValue
Range10 - 200 nm
Default50 nm
Unitnm

Physical Significance:

Junction depth affects the characteristic length:

Good SCE control requires .

Effects:

Shallower Deeper
↓ SCE↑ SCE
↑ Series resistance↓ Series resistance
↓ Junction capacitance↑ Junction capacitance

LDD Doping ( ) ​

PropertyValue
Range10¹⁷ - 10²⁰ cm⁻³
Default5×10¹⁸ cm⁻³
Unitcm⁻³

Purpose:

Lightly Doped Drain (LDD) extensions:

  • Reduce peak electric field at drain
  • Mitigate hot carrier effects
  • Improve reliability

LDD Length ( ) ​

PropertyValue
Range5 - 50 nm
Default20 nm
Unitnm

Trade-offs:

Longer LDDShorter LDD
↓ Peak E-field↑ Peak E-field
↑ Series resistance↓ Series resistance
Better HCI immunityWorse HCI immunity

Substrate ​

Substrate Doping ( ) ​

PropertyValue
Range10¹⁴ - 10¹⁸ cm⁻³
Default10¹⁷ cm⁻³
Unitcm⁻³

Physical Significance:

Sets the body effect coefficient:

And depletion width:

Geometry ​

Channel Width ( ) ​

PropertyValue
Range50 - 2000 nm
Default360 nm (nMOS), 720 nm (pMOS)
Unitnm

Physical Significance:

Width directly scales current:

PMOS Sizing

PMOS is typically 2× wider than NMOS to compensate for lower hole mobility:

Gate-S/D Overlap ( ) ​

PropertyValue
Range0 - 20 nm
Default5 nm
Unitnm

Effects:

  • Contributes to overlap capacitance:
  • Affects Miller effect in switching
  • Reduces effective channel length

Advanced Parameters ​

Fixed Oxide Charge ( ) ​

PropertyValue
Range±10¹² cm⁻²
Default0
Unitcm⁻²

Effect:

Shifts flat-band and threshold voltage:

Positive charge shifts negative.

Interface Trap Density ( ) ​

PropertyValue
Range0 - 10¹³ cm⁻² eV⁻¹
Default0
Unitcm⁻² eV⁻¹

Effects:

  • Increases subthreshold swing
  • Causes frequency dispersion in C-V
  • Degrades mobility (Coulomb scattering)

Series Resistance ( , ) ​

PropertyValue
Range0 - 1000 Ω
Default0
UnitΩ

Effects:

  • Reduces effective :
  • Limits maximum current
  • Causes negative feedback

Components:

  • Contact resistance
  • Silicide resistance
  • LDD resistance
  • Spreading resistance

Parameter Scaling Guidelines ​

For scaling to a new technology node:

ParameterScaling Factor45nm → 28nm
0.7×45 → 28 nm
0.7×180 → 120 nm
0.8×1.5 → 1.2 nm
0.9×1.0 → 0.9 V
0.7×30 → 20 nm
1.4×10¹⁸ → 2×10¹⁸ cm⁻³

Non-Ideal Scaling

Real scaling is constrained by:

  • Gate leakage (can't scale indefinitely)
  • Threshold variation (limits scaling)
  • Power density (thermal limits)